RISCV ISA in 10 minutes
Specifications:
- Volume 1, Unprivileged Spec v. 20191213 [PDF]
- Volume 2, Privileged Spec v. 20211203 [PDF]
- Recently ratified, but not yet integrated, extension specifications
Registers
Integer registers
The width of these registers is set by the XLEN property of the implementation (e.g. 32 for 32bit implementations and 64 for 64bit implementation).
| 5-bit Encoding | 3-bit Compressed Encoding | Register | ABI Name | Description | Saved by Calle- |
|---|---|---|---|---|---|
| 0 | - | x0 | zero | hardwired zero | - |
| 1 | - | x1 | ra | return address | -R |
| 2 | - | x2 | sp | stack pointer | -E |
| 3 | - | x3 | gp | global pointer | - |
| 4 | - | x4 | tp | thread pointer | - |
| 5 | - | x5 | t0 | temporary register 0 | -R |
| 6 | - | x6 | t1 | temporary register 1 | -R |
| 7 | - | x7 | t2 | temporary register 2 | -R |
| 8 | 0 | x8 | s0 / fp | saved register 0 / frame pointer | -E |
| 9 | 1 | x9 | s1 | saved register 1 | -E |
| 10 | 2 | x10 | a0 | function argument 0 / return value 0 | -R |
| 11 | 3 | x11 | a1 | function argument 1 / return value 1 | -R |
| 12 | 4 | x12 | a2 | function argument 2 | -R |
| 13 | 5 | x13 | a3 | function argument 3 | -R |
| 14 | 6 | x14 | a4 | function argument 4 | -R |
| 15 | 7 | x15 | a5 | function argument 5 | -R |
| 16 | - | x16 | a6 | function argument 6 | -R |
| 17 | - | x17 | a7 | function argument 7 | -R |
| 18 | - | x18 | s2 | saved register 2 | -E |
| 19 | - | x19 | s3 | saved register 3 | -E |
| 20 | - | x20 | s4 | saved register 4 | -E |
| 21 | - | x21 | s5 | saved register 5 | -E |
| 22 | - | x22 | s6 | saved register 6 | -E |
| 23 | - | x23 | s7 | saved register 7 | -E |
| 24 | - | x24 | s8 | saved register 8 | -E |
| 25 | - | x25 | s9 | saved register 9 | -E |
| 26 | - | x26 | s10 | saved register 10 | -E |
| 27 | - | x27 | s11 | saved register 11 | -E |
| 28 | - | x28 | t3 | temporary register 3 | -R |
| 29 | - | x29 | t4 | temporary register 4 | -R |
| 30 | - | x30 | t5 | temporary register 5 | -R |
| 31 | - | x31 | t6 | temporary register 6 | -R |
Floating point registers
The width of these registers is set by the FLEN property of the implementation (e.g. 32 for single presicion, 64 for double precision and 128 for quad precision).
| Register | ABI Name | Description | Saved by Calle- |
|---|---|---|---|
| f0–7 | ft0–7 | FP temporaries | -R |
| f8–9 | fs0–1 | FP saved registers | -E |
| f10–11 | fa0–1 | FP arguments/return values | -R |
| f12–17 | fa2–7 | FP arguments | -R |
| f18–27 | fs2–11 | FP saved registers | -E |
| f28–31 | ft8–11 | FP temporaries | -R |
Unprivileged ISA
The following Unprivileged ISA modules are either ratified or frozen in the The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20191213.
| Module | Description |
|---|---|
| RVWMO | RISCV Weak Memory Ordering (Memory Consistency Model) |
| RV32I | 32Bit (XLEN=32) Base Integer Instruction Set |
| RV64I | 64Bit (XLEN=64) Base Integer Instruction Set |
| Zifencei | FENCE.I explicit synchronization between writes and fetches |
| Zicsr | Control and Status Register (CSR) Instructions |
| M | Integer Multiplication and Division Instructions |
| A | Atomic Instructions |
| F | Single-Precision Floating-Point (FLEN=32) Instructions |
| D | Double-Precision Floating-Point (FLEN=64) Instructions |
| Q | Quad-Precision Floating-Point (FLEN=128) Instructions |
| C | Compressed Instructions |
| Ztso | Total Store Ordering |
Compressed Instructions
The compressed instructions are 16 bits long, which can be expanded to regular instructions. Ghidra for example uses the compressed mnemonic (i.e. c.*) whereas IDA shows the expanded mnemonic.